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processes.Proven experience in maintaining EDA tools and managing PDKs (Cadence, Synopsys, Mentor Graphics).Hands-on experience with IC testers and emulators for pre-silicon verification.Strong understanding of semiconductor fabrication processes, including...
R&D Engineer II - C++ & Computational Geometry
Date: Sep 18, 2025
Company: Ansys
Requisition #: 17225
Ansys is now a part of Synopsys. Synopsys, Inc. (Nasdaq: SNPS) accelerates technology innovation from silicon to systems. Catalyzing the era of...
con formal verification (SVA/PSL, Cadence Jasper, Synopsys VC Formal)
Laurea magistrale in Ingegneria Elettronica / Informatica
(o equivalente)
Verifica low-power con UPF/CPF
Padronanza di SystemVerilog, UVM e tool
di simulazione (Cadence Xcelium...
or semiconductor processes.
• Proven experience in maintaining EDA tools and managing PDKs (Cadence, Synopsys, Mentor Graphics).
• Hands-on experience with IC testers and emulators for pre-silicon verification.
• Strong understanding of semiconductor...
da netlist RTL, definendo macro
placement, channel e power grid.
• Place-&-Route (Cadence
Innovus, Synopsys ICC2/ Fusion Compiler, Siemens Aprisa) con focus su
congestione, timing e DRC.
• Clock-Tree
Synthesis (CTS) e ottimizzazione di skew, jitter...